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revision history AS6C3216A-55TIN 48pin-tsop i package revision details date rev 1.0 initial issue mar. 2017 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS6C3216A-55TIN confidential - 1 of 12 - rev.1.0. mar. 2017
features n fast access time : 55ns n low power consumption: operating curren t : 12 ma ( typ .) standby current : 8 a( typ . ) sl- version n single 2.7v ~ 3.6v power supply n al l inputs and outputs ttl compatible n fully static operation n tr i- state output n data byte control : (i ) byte# fixed to v cc dq0 ~ dq7 controlled by lb#, dq8 ~ dq15 controlled by ub#. (ii ) byte# fixed to v ss dq15 used as address pin, while dq8~dq14 pins not u sed . n data retention v oltage : 1.2v (min.) n rohs compliant n package : 48- pin 12mm x 20mm tsop i general description the AS6C3216A-55TIN is a 33,554,432-b it low power cmos s tatic random access memory organized as 2,097,152 words by 16 bits or 4,194,304 words by 8 bits . it is fabricated using v ery high performance, high reliability cmos technology. its standby current is s table within the range of operating temperature. the AS6C3216A-55TIN is well designed for low power application, and particularly well suited for battery back-u p nonvolatile memory application. the AS6C3216A-55TIN operates from a single power s upply of 2.7v ~ 3.6v and all inputs and outputs are fully ttl compatible product family product family operating te m p e r a t u r e v cc range speed p ower dissipation standby( i sb1 , typ.) operating( i cc ,typ.) AS6C3216A-55TIN -4 0 ~ 85 2.7 ~ 3.6v 55ns 8a 12ma orwerinu inporatcion package type access time (speed)(ns) power type te m p e r a t u r e range() packing type alliance memory part number 48- pin tsop i ( 12mm x 20mm ) 55 special ultra low power -4 0 ~85 tray AS6C3216A-55TIN ta p e r e e l AS6C3216A-55TIN tr AS6C3216A-55TIN confidential - 2 of 12 - rev.1.0. mar. 2017
functional block diagram control circuit decoder 2048kx16 memory array column i/o a0~a20 /a-1~a20 v cc v ss dq 8- dq 15 upper byte dq 0- dq 7 lower byte i/o data circuit ce 2 we# oe# lb# ub # ce # byte# pin description symbol description a0 C a2 0 address inputs (word mode) a-1 C a 20 address inputs (byte mode) dq0 C dq15 data inputs/outputs ce# , ce2 chip enable input we# write enable input oe# output enable input lb# lower byte control ub# upper byte control byte # byte enable v cc power supply v ss ground pin configuration tsop i a15 a14 a13 a12 a8 AS6C3216A-55TIN xxxxxxxx xxxxxxxx 8 7 6 5 4 3 2 1 a11 a10 a9 a20 a19 we# ce2 nc ub# lb# a18 a17 a7 a6 a5 a4 a3 a2 a1 14 13 12 11 10 9 16 15 22 21 20 19 18 17 24 23 dq13 byte# dq15/a-1 dq7 dq14 dq6 44 41 42 43 a16 v ss 48 47 45 46 33 36 35 34 38 39 40 37 25 28 27 26 30 31 32 29 dq12 dq5 dq4 v cc dq11 dq3 dq10 dq2 dq1 dq9 dq8 dq0 oe# v ss ce# a0 AS6C3216A-55TIN confidential - 3 of 12 - rev.1.0. mar. 2017
absolute maximum ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 - 0.5 to 4.6 v voltage on any other pin relative to v ss v t2 - 0.5 to v cc +0.5 v operating temperature t a -40 to 85 (i grade) storage temperature t stg - 65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stre s s rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device re lia bility. truth table mode ce# c e2 byte# oe# we# lb# ub# i/o operation supply current dq0 - dq7 dq8 - dq14 dq15 standby h x x x l x x x h x x x x x x x x h x x h high C z high C z high C z high C z high C z high C z high C z high C z high C z i sb1 output disable l l l h h h h h l h h h h h h l x l x l l high C z high C z high C z high C z high C z high C z high C z high C z a-1 i cc ,i cc1 read l l l h h h h h h l l l h h h l h l h l l d out high C z d out high C z d out d out high C z d out d out i cc ,i c c1 write l l l h h h h h h x x x l l l l h l h l l d in high C z d in high C z d in d in high C z d in d in i cc ,i cc1 byte# read l h l l h l l d out high C z a-1 i cc ,i cc1 byte # write l h l x l l l d in high C z a-1 i cc ,i cc1 note: h = v ih , l = v il , x = don't c are. AS6C3216A-55TIN confidential - 4 of 12 - rev.1.0. mar. 2017
dc electrical characteristics parameter symbol test condition min. typ. *4 max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih *1 2. 2 - v cc +0. 3 v input low voltage v il *2 - 0. 2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage c urrent i lo v cc R v out R v ss output disabled - 1 - 1 a output high voltage v oh i oh = - 1ma 2. 2 2.7 - v output low voltage v ol i ol = 2 ma - - 0.4 v average operating power supply cur rent i cc cycle time = min. ce# Q 0.2v and ce2 R v cc - 0.2v i i/o = 0ma o ther pins at 0.2v or v cc - 0.2v - 12 20 ma i cc1 cycle time = 1 s ce# Q 0.2v and ce2 R v cc - 0.2v i i/o = 0ma o ther pins at 0.2v or v cc - 0.2v - 3 5 ma standby power supp ly current i sb1 ce# R v cc - 0.2v or ce2 Q 0.2v o ther pins at 0.2v or v cc - 0.2v a *6 - 8 18 - - 50 no tes: 1. v ih (max) = v cc + 2 .0 v for pulse width less than 6 ns. 2. v il (min) = v ss - 2 .0 v for pulse width less than 6 ns. 3. over/undershoot specifications are characterized on engineering evaluation stage , not for mass production test . 4. typical values , measu red at v cc = v cc (typ.) and t a = 25 , are included for reference only and are not guaranteed or tested. 5 . t his parameter is measured at v cc =3.0v . 6 . t his parameter is measured at t a = 70 capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. max unit input capacitance c in - 8 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0 .2 v to v cc - 0.2 v input rise and fall time s 3 ns input and output timing reference levels 1.5v output load c l = 3 0pf + 1ttl , i oh /i ol = - 1ma/ 2 ma a *5 AS6C3216A-55TIN confidential - 5 of 12 - rev.1.0. mar. 2017
ac electrical characteristics (1) read cycle parameter sym . AS6C3216A-55TIN unit min. max. read cycle time t rc 55 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe - 30 ns chip enable to output in low -z t clz * 10 - ns output enable to output in low -z t olz * 5 - ns chip disable to output in high -z t chz * - 20 ns output disable to output in high -z t ohz * - 20 ns output hold from address change t oh 10 - ns lb#, ub# a c cess time t ba - 55 ns lb#, ub# to high - z output t bhz * - 20 ns lb#, ub# to low - z output t blz * 10 - ns (2) write cycle parameter sym . AS6C3216A-55TIN unit min. max. write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set - up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overlap t dw 25 - ns data hold fr om end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high -z t whz * - 20 ns lb#, ub# valid to end of write t bw 50 - ns *these parameters are guaranteed by device characterization, but not production tested. AS6C3216A-55TIN confidential - 6 of 12 - rev.1.0. mar. 2017
timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 ( ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid high-z high-z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace t ba t blz ce# t aa address t rc ce2 notes : 1. we# is high for read cycle. 2.device is continuously selected oe# = low , ce# = low, ce2 = high, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, ce2 = high, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz , t olz , t chz , t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz . AS6C3216A-55TIN confidential - 7 of 12 - rev.1.0. mar. 2017
write cycle 1 ( we# controlled) (1,2, 4 ,5) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow lb#,ub# t bw ce# t aw address t wc ce2 write cyc le 2 ( ce# and ce2 c ontrolled) (1, 4 ,5) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t wp t bw ce# address t wr t as t aw t wc ce2 AS6C3216A-55TIN confidential - 8 of 12 - rev.1.0. mar. 2017
write cycle 3 ( lb# , ub# controlled) (1, 4 ,5) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t as t wp t bw ce# address t wr t aw t wc ce2 notes : 1 .a write occurs during the overlap of a low ce#, high ce2, low we#, lb# or ub# = low. 2 .during a we# con trolled write cycle with oe# low , t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 3 .during this period, i/o pins are in the output state, and input signals must not be applied. 4 .if the ce#, lb#, ub# l ow transition and ce2 high transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance state. 5 .t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. AS6C3216A-55TIN confidential - 9 of 12 - rev.1.0. mar. 2017
data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# R v cc - 0.2v or ce2 Q 0.2v 1. 2 - 3.6 v data retention current i dr v cc = 1.2 v ce# R v cc - 0.2v or ce2 Q 0.2v other pins at 0.2v or v cc - 0.2v - 6 .5 16 a - - 50 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc* - - ns t rc* = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr ? 1.2v ce# ? v cc -0.2v vcc (min.) v ih t r t cdr v ih v cc (min.) low vcc data retention waveform (2) ( ce2 controlled) vcc ce2 v dr ? 1.2v ce2 ?? 0.2v vcc (min.) v il t r t cdr v il v cc (min.) lo w vcc data retention waveform ( 3) ( lb# , ub# controlled) vcc lb#,ub# v dr ? 1.2v lb#,ub# ? v cc -0.2v vcc (min.) v ih t r t cdr v ih v cc (min.) AS6C3216A-55TIN confidential - 10 of 12 - rev.1.0. mar. 2017
package outline dimension 48- pin 12mm x 20mm tsop i package outline dimension AS6C3216A-55TIN confidential - 11 of 12 - rev.1.0. mar. 2017
part numbering system a s6c 3216a 55 t i n low power s ram 32 = 32m 16 = x16 a = a die 55=55ns t = tsopi i= industrial ( - 40 c~+ 8 5 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS6C3216A-55TIN confidential - 12 of 12 - rev.1.0. mar. 2017

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